The present invention relates to a ΔΣ-type AD converter arranged so as to exhibit a high dynamic range while a ΔΣ-modulated sampling frequency is suppressed to a comparatively-low level. The present invention also provides a class-D amplifier and a DC-DC converter which utilize the ΔΣ-type AD converter.
FIG. 2 shows a related-art ΔΣ-type AD converter. A subtractor 10 subjects an analogue input signal and a feedback signal to subtraction. An integrator 14 integrates a signal output from the subtractor 10. A quantizer 16 compares a signal output from the integrator 14 with a predetermined threshold value, thereby binarizing the signal. A signal output from the quantizer 16 is a one-bit digital signal which assumes a value of “1” or “0” at a sampling interval unit of ΔΣ modulation, and the one-bit digital signal is subjected to analogue-to-digital conversion, and a result of conversion is output. The one-bit digital signal is subjected to one sample delay by means of a one sample delay circuit 12, and the thus-delayed signal is fed back as the feedback signal to the subtractor 10. ΔΣ-type AD converters, such as those described in; for example, Patent Documents 1 and 2, are available as a related-art ΔΣ-type AD converter.
[Patent Document 1] JP-A-2000-174627
[Patent Document 2] JP-B-2856117
A dynamic range of the ΔΣ-type AD converter changes according to a sampling frequency, and a required dynamic range has hitherto been ensured by means of increasing the sampling frequency. However, as a result of an increase in the sampling frequency, an operational amplifier capable of making a high-speed response over a wide range is required as an operational amplifier used in an integrator, which adds to cost.